Selected work

Project

04 of 06

Discipline

Embedded

Gendio Display Controller

An ESP32-S3 controller design combining a custom four-layer PCB, serial data handling, matrix-display firmware and a local browser interface.

PCB design render showing the ESP32-S3 processor, power section and interface connectors.
PCB design renderFull-size image ↗

Problem

An industrial weight display needs a controller that translates serial data into clear, consistent readings and gives technicians a straightforward way to configure it.

Architecture

Serial inputs feed a parser and receiver state machine. Display formatting and scanning are separated from configuration and update handling. The PCB design brings together power conversion, processing, serial interfaces and display buffering.

Design decisions

  1. Kept display outputs disarmed after boot until explicitly enabled through the configuration workflow.
  2. Separated serial parsing, receiver state and display scanning so each could be exercised independently.
  3. Reviewed footprints, connector drills and component dissipation. Corrected a fuse footprint and increased the termination resistor rating.
  4. Added fallback glyphs and blanking for invalid display rows, with host-based regression tests.

Verification

Verification covered the firmware build, synthetic serial-protocol fixtures, host-based display tests, browser workflows and circuit modelling. These checks supported the PCB and software development.

Engineering case study

Read the design rationale, verification scope and proposed next experiments.

Read the Gendio Display Controller case study

Development and testing

Schematic and PCB review

Reviewed schematic connectivity, footprints and connector drills in KiCad, including corrections to the fuse footprint and termination resistor rating.

Firmware build

Compiled the ESP32-S3 firmware and checked image identity, partition placement and non-overlap.

Serial protocols

Exercised fragmentation, corruption, timeouts, recovery and counter wraparound across 31 synthetic protocol profiles.

Display logic

Host framebuffer and GPIO simulations checked glyph fallback, clipping, mirroring, row addressing, clock pulses, disarming and invalid-row blanking.

Browser interface

Tested 31 protocol options and five configuration workflows against a mocked API, including JavaScript error and mobile overflow checks.

Circuit modelling

Used ngspice for divider corners, reset timing and fixed-duty LC studies, with GNU Octave for analytical load-step and tolerance calculations.

Mechanical exports

Prepared the board model and mounting exports and matched 88 SMT designators against the placement file.

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